Integrated power electronics
Delivering power to integrated circuits is becoming an increasingly complex challenge. On the high end, chips can demand in excess of 150 W of power at supply voltages of less than 1 V, leading to current demands approaching 200 A. We have been developing on-chip DC-DC conversion approaches that allow power to be delivered to chips at higher voltages and lower current levels. Such technology will enable improved efficiency by reducing I2R losses in the power distribution network, reducing required voltage tolerances with improved regulation and facilitating system-level power saving techniques such as dynamic voltage and frequency scaling. Recently, we have been exploring various strategies to enable switched-inductor integrated voltage regulation, with the aim of eventually fabricating custom power inductors, using laminations of high quality magnetic material (shown left), which will enable high current density integrated power conversion.
- N. Sturcken, M. Petracca, S. Warren, L. P. Carloni, A. V. Peterchev and K. L. Shepard, "An integrated four-phase buck converter delivering 1A/mm2 with 700ps controller delay and network-on-chip load in 45-nm SOI," Custom Integrated Circuits Conference (CICC), September, 2011
- S. Rajapandian, K. L. Shepard, P. Hazucha, and T. Karnik, "High-voltage power delivery through charge recycling," IEEE Journal of Solid-State Circuits, June, 2006
- S. Rajapandian, Z. Xu, and K. L. Shepard, "Implicit dc-dc downconversion through charge recycling," IEEE Journal of Solid-State Circuit, April, 2005
- S. Rajapandian, K. L. Shepard, P. Hazucha, and T. Karnik, "High-tension power delivery: operating 180-nm CMOS digital logic at a 5.4-V supply," Digest of Technical Papers, International Solid-State Circuits Conference, 2005.
- S. Rajapandian, Z. Xu, and K. L. Shepard, "Energy-efficient, low-voltage operation of digital CMOS circuits through charge-recycling," Symposium on VLSI Circuits, 2004