BIOEE | On-chip circuit for measuring period jitter and skew of clock distribution networks

K. A. Jenkins, K. L. Shepard, and Zheng Xu, “On-chip circuit for measuring period jitter and skew of clock distribution networks” IEEE Custom Integrated Circuits Conference, 2007.

Abstract

A circuit for on-chip measurement of period jitter and skew of clock distribution is described. The circuit uses a single latch and a voltage-controlled delay element. The circuit is evaluated in a stand-alone pad frame, where a jitter resolution of about 1 ps is demonstrated, and is incorporated in a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurement.