Functional verification using .vec files

 

If you haven't read the CAD tool information page, READ THAT FIRST.

Vector file is a very convenient way to do functional verification for large scale digital circuits. In a vector simulation, you can easily assign a set of input patterns at different time, and the simulator will automatically generate piece wise linear voltage sources (vpwl) connected to assigned wires. You could also include expected output patterns in vector files, and then the simulator can tell whether the output of the circuit matches what you expect or not.

Let's go through the following example and see how it works.



Example using 2-input NAND gate

To begin with, let's first use a simple NAND gate to demonstrate how vector files work and the basic syntax.

Step 1: Draw the schematic of the NAND gate. Here I use 2u/100n for both pFET's and nFET's.

Step 2: Set up the test bench for this NAND gate with cell name NAND_tb . There are two inverters (pFET 2u/100n, nfet 1u/100n) in front of each input working as a buffer.

Step 3: Open ADE L. Under Setup -> Simulator/Directory/Host ... , make sure you have UltraSim as your simulator. The following steps assumes you use /space/yourUNI as your Project Directory . Also, don't forget to setup your model library as before.

Step 4: Choose a place where you would like to store your vector files, say ~/Cadence/vec , and create a new file called nand.vec under this directory with following content:

; Note: lines start with this symbol represents comment
; Last revision: Nov. 26 2015
; Author: Yihan Zhang

; Enable waveform output, so that you can still see waveforms in your simulation
output_wf 1

; RADIX specifies the number of bits of each vector
radix 1 1 1

; VNAME assigns name to your vector.
vname A B Out

; IO specifies the direction (input/output) of a vector
io i i o

; TUNIT means any number representing time will have the following unit
tunit 10ps

; CHK_WINDOW specifies the window that the simulator will check for your output
chk_window -19 20 1 period=20

; PERIOD specifies the period of your signal
period 20

; TRISE and TFALL specifies the rising time and falling time
trise 2
tfall 2

; VIH and VIL specifies input high voltage and low voltage respectively
vih 1.2
vil 0.0

; VOH and VOL specifies output high voltage and low voltage respectively
voh 0.7
vol 0.5

; Tabular vector data
1 1 0
1 0 1
0 1 1
0 0 1
1 1 0

Basically what this vector file does is to set the voltage value of A and B for each 200ps period to be the numbers in the first two columns in the tabular data. And we want to check if the output matches what is listed in the third column. We will further explain what these lines mean and how to modify them later.

Step 5: Go to Setup -> Simulation Files ... , under tab Vector Files , add the file you just created. For this example, it is ~/Cadence/vec/nand.vec

Step 6: Now click on Choose Analysis , setup an tran simulation of 1.5ns. Basically anytime longer than the time you need to finish the simulation pattern specified in your vector file is fine. For this example, the minimum time is 1ns.

Step 7: Click Netlist and Run . You should get no error in the simulation.

Step 8: Open Tools -> Results Browser , and check the results. Under folder tranVECERR , you can see if there is any output that doesn't matches your expetation. Once such error happens, the error waveform of the output wire will turn to one at the corresponding time period. Under folder tranVECEXP , you will be able to see what the vector file expects to see at the output. If the reason of the error is that you are expecting the wrong result, then you need to change your vector file.

Now you know the basic work flow of a vector simulation. Let's take a closer look at the statements in the vector file.



A closer look at vector file format

1. How does a vector file assign inputs into the circuit: This is implemented by statement vname. During simulation, wires with the names follow the statement will be created. If you have a wire with the same name inside your design (netlist), they will be automatically connected together.

2. How does the vector file know the Vdd of the circuit: This is what you need to tell the vector file. The command vih and vil tell the vector file to use 1.2 volt as input 1, and 0.0 volt as input 0 in the example. The command voh and vol tell the vector file to treat any voltage above 0.7 volt as an output 1, and below 0.5 volt as an output 0.

3. How do I assign patterns at a specific time: First of all, the statement tunit specifies the unit of all numbers related to time. It could be whatever number suffixed with ps, ns, etc. In the example where we used 10ps as our time unit, the period is then 200ps, and rising and falling slew of the input is 20ps. The tabular data at the end of the vector file is then consists of the data you want to assign to the input, and check from the output.
Specific time could be added before each row of the vector, for example:

0 1 1 0
20 1 0 1
40 0 1 1
60 0 0 1
80 1 1 0

This is equivalent to using the statement period, thus the time for each row will be automatically set to be 0*period, 1*period, 2*period, ....

4. How can I assign input to buses using vector file: You could modify the radix command. Vector files support radix up to 4. If you have 8 input wires named I7, I6, ..., I0, and 4 outputs named O3, O2, O1, O0 then what you can do is:

radix 4 4 4
vname I[7:4] I[3:0] O[3:0]
io i i o
...
0 0 0
F F F
...

In cadence, buses are usually named as A<7:0>. In vector files, you should then write A<[7:4]> A<[3:0]> to assign them with the value you want.

5. How does vector file check the output: The command chk_window tells the vector file how to check the output based on the tabular data you have for each output node. The command has a syntax as follows:

chk_window start_time end_time steady [period=const [first=const]] mask1 mask2 ...

What this command do is to let the simulator check, from vec_time-start_time to vec_time+end_time if the output matches what you expect. The value of vec_time is determined by the option period and first as:

vec_time = first + n*period

If steady is 1, then the result won't be seen as correct unless the output signal is held at digital one throughout the entire checking window. It is very likely to get this command wrong. One easy way to verify if it is the way this check window is mistakenly defined when you get an error after the simulation, is to take a look at Project Directory/yourCellName/UltraSim/schematic/psf/netlistName.vecerr. In the example, it is /space/yourUni/NAND_tb/UltraSim/schematic/psf/input.vecerr. Below the general information about your setup, you will find error messages like this:

****VectorCheck for Out:
From 1.900000e-10 to 2.100000e-10, Expected state = one, Actual state = zero
From 7.900000e-10 to 8.100000e-10, Expected state = zero, Actual state = one

Looking at this, you will be able to tell if it is a mistake with the checking window, or the output state itself is wrong.



More reference

For more and detailed reference, you can take a look at UltraSim simulator user guide.



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