Creating Full custom Layouts using Cadence' Virtuoso Layout Editor
 

 


In this handout, we are going to learn the following :

By now, you would have known how to enter and simulate your designs using Spectre.  The next step in the process of making an integrated circuit chip is to create a layout.  What is a layout?  A layout is basically a drawing of the masks from which your design will be fabricated.  Therefore, layout is just as critical as specifying the parameters of your devices because it determines whether yours is a working design or a flop!

There are 2 ways of doing a layout: manual and automated.  Manual layout usually enables the designer to pack his devices in a smaller area compared to the automated process but it is more tedious.  The automated process, on the other hand, is done using standard cells and usually takes more real estate space but it is much faster.  In this tutorial, you will learn how to perform manual layouts and a simple inverter layout will be shown.

Before we get into the layout, first you need to understand the design rules for layout.  The design rules which we will be using is the IBM 90nm CMOS Rules. Design rules give guidelines for generating layouts. They dictate spacings between wells, sizes of contacts, minimum spacing beween a poly and a metal and many other similar rules. Design rules are essential to any successful layout design, since they account for the various allowances that need to be given during actual fabrication and to account for the sizes and the steps involved in generating masks for the final layout. The design rules that we will be using can be found on the VLSI lab computers at /courses/ee4321/tech/cms9flp/IBM_PDK/cms9flp/relIBM/doc/cms9flp.design_manual.pdf . You can read pdf's directly in the command window by typing (evince filename.pdf). Note that the layout is very much process dependent , since every process has a certain fixed number of available masks for layout and fabrication. For the case of this tutorial, we are using a IBM 90nm CMOS process, which is an nwell process and supports one poly and more than eight metal layers.

Before we proceed any further, we must specify the tech file that we will be using when running DRC and LVS checks. In your CIW window, go to IBM_PDK --> Library --> Add IBM_PDK Lib Properties. At the new window, for 'Library Name', choose 'yourUNI'. For 'Technology', choose 'cmf9flp', and for 'Number of levels of metal', choose '6_02_00_00_LB' as in the figure below.

 

 

 

1.  Here we will create a layout for the inverter cell.
In the CIW window, click on the File --> New --> CellView.  Choose Library as 'yourUNI', CellName as 'inverter' and View Name as 'layout'. Make sure that type is 'layout' and Open with is 'layout L' . Then click on the OK button.   The LSW window will show all the layers like nwell, pwell, active etc. for the given process. An alternate way to open the  layout editor window is to click on "Layout" in the View window for inverter cell in the Library manager window. Then click on File --> Open.

The LSW window should look something like this:


 
 

 

If LSW looks different, then the most probable error is that your library is not attached to the Technology Library "cms9flp". You should attach you library to this technology file as described earlier in this page.

We are ready to draw objects in the layout window. Go to Create-> Instance . Take the nfet device from Library Browser as it is shown below.  Do not forget to pick layout view. After you place the transistors on the layout window, you can change the sizes by clicking on your transistor with your mouse and then you can press Q on your keyboard.

 

Then, we need to create the necessary pins as well. Go to Create -> Pin.

1-For the input, write the terminal name as 'in'.Select the mode as manual. Pick the I/O type as input. Put a checkmark on Create Label and select auto. After that, click on options. You can write height as 0.2 . Then, click OK. Then, Select M1 pin from the LSW window.  Then, draw a rectangle with mouse's left click. Do not size the rectangle too big or small. (You can see a proper size for a pin on the following screenshots.) Place the pin somewhere available on the layout window. Click on the 'text' on the pin that you created, make sure the layer is M1 layer.

2-For the output, write the terminal name as 'out'. Pick the I/O type as output. Then, draw the pin on layout window as it was explained for the input.

3-For the vdd, write the terminal name as 'vdd!'. Pick the I/O type as inputOutput. Then, draw the pin on layout window as it was explained for the input.

4-For the ground, write the terminal name as 'gnd!'. Pick the I/O type as inputOutput. Then, draw the pin on layout window as it was explained for the input.

*don't worry, your your pins will be 'blue' unlike the above layout.

Try to move the transistors by hitting 'm' and clicking the component. You will see that the components do not move freely. Instead, they will move along certain angles and snap to the grid. Therefore, for better cursor movement, it is crucial to follow these steps:

1. Go to Options --> Display and at the box at the top right, check Grid off. Below, enter 0.01 for 'Minor Spacing' and 0.1 for 'Major Spacing'. Then insert 0.01 for both 'X snap spacing' and 'Y snap spacing'. Below that, at the box named 'Snap Modes', choose 'Create: anyAngle' and 'Edit: orthogonal'. You can save these settings by doing 'Save to' and pressing OK.

2. Go to  Options --> Editor  and at the top middle box, check 'none' for 'gravity'.

Now that you have placed all components, you need to make connections between them to create an inverter. We also need to place substrate and n-well contacts.  Before drawing any wires, you need to select the correct drawing layer from the layer selection window (LSW) .  First choose "M1 drw" from LSW . Now try drawing some wires with  create --> shape --> rectangle (shortcut 'r')  or   create --> shape --> path (shortcut 'w'). Note that drawing paths is a little tricky. You will need to practice a little bit. To end a path you have to double click with your left mouse button.

Generally drawing rectangles are easier to draw and edit. If you have drawn a rectangle of any layer and need to edit its location or dimensions, press 's', then drag your cursor into a box enclosing the specific part that you want to edit. For instance, you can enclose a corner, or you can enclose an edge of the rectangle and edit accordingly.

Now add in the wire connecting the drains of both nmos and pmos which will serve as the output of the inverter. Do the same for the poly connection between the gates. You can do this by choosing "pc drw" from LSW. Note that create --> shape --> path  automatically chooses min. width for the path. To change this, you need to hit F3 while the command is active and an option form will appear in which you can change the width. By using  'rectangle' or 'path' , you can also make vdd and gnd buses (vdd on top of pmos and gnd on bottom of nmos) with metal layer M1. Also connect the source of pmos to this vdd bus and that of nmos to gnd bus using the 'M1 drw' layer. Note that everything is manual when drawing layouts; connecting the substrate of the pmos to Vdd should be done by hand as well. Extend the n-well of the pmos to reach into the vdd bus on the top. You can do this by using the 'NW drw' layer.

One useful tool is the ruler. You can draw a ruler by hitting 'k'. With it you can align the vdd and gnd buses, and keep there sizes symmetrical. To remove all rulers on the screen, press shift + k.

* If you are in the middle of any command such as 'm', 'w' or 's', hit F3 and an option form will appear specifically for that command. You can generally solve most of the problems by choosing various options from this form which can be applied to the currently active command.

 

Then move your pins to the correct location. Have each pin in contact with an M1 layer of the same net. So your VDD pin, for instance, can be anywhere on top of your VDD bus. One important fact here is to make sure that the label moves with the pin. Each label (the pin name in text) will have an 'x' mark in its center. If this 'x' mark is not on top of the same net that the pin is, you will get an error in LVS saying 'Abort on supply error'.

 

Now we should add vias (also called contacts), which are vertical connections between two different layers. For example, an M1_M2 via would enable conduction between the two metal layers M1 and M2. To place the substrate and n-well vias, choose  create --> via . From the tab that says 'via Definition', you can choose the via that you want to use. In our inverter layout, we will need three vias: 

1) connecting the 'IN' pin made of the M1 layer with the two gates made of the PC layer  
2) connecting the n-well with the VDD bus M1 layer  
3) connecting the NMOS substrate with the GND bus at the bottom

The three locations are shown below.

 

 

To add Via 1, go to Create --> Via, and select VPC_M1. Place it touching both the PC layer (red) between the two gates AND the M1 layer (blue). As you see below, there must be some area of the pc layer of layout overlapping with the pc layer of via; similarly, there must be some area of the M1 layer of layout overlapping with the M1 layer of via. An easy way to do this is to have the PC and M1 layers overlapping in the first place, and then placing the via where they overlap.

 

 

Before we draw Vias 2 and 3, there are two layers to study: The RX layer (green) and the BP layer (red slashes). The layer 'RX' is the 'active layer'. It is where the doping takes place, to form Source and Drain areas for instance. If the active layer is on top of a BP layer, it represents a p-type diffusion area; if the active layer is not on top of a BP layer, it represents an n-type diffusion area.

 

 

Source: http://en.wikipedia.org/wiki/File:Cmos_impurity_profile.PNG

 

The drawing above shows us a sideview of a Pfet and Nfet put together. For the Nfet, the substrate will be of p-type and it should be connected to GND. So we will do this with a RX + BP layer connected to the GND metal layer. (Via 3)
For the Pfet, the substrate will be of n-type and it should be connected to Vdd. So we will do this solely with the RX layer. However, now this needs to connected to the n-well of the Pfet. (Via 2)

Let's place Via 2 first. First draw an n-well overlapping a little with the n-well of the Pfet and covering much of the VDD bus. Use the metal layer 'nw drw'. Now add a via connecting the RX(active) layer and the M1 layer on top of the Vdd bus, where M1 and NW overlap. The Via you should look for is "VRX_M1" or "VDRX_M1". The letter 'D' simply makes a via double the size, which then reduces the resistance through the contact. As long as geometric constraints allow you to, try to use a larger via to reduce parasitic resistance.

Similarly, this time we can connect the bulk of the Nfet with GND (Via 3). This time we need the bulk to be of the p-type, so we need both the active layer and the BP layer. First place a VDRX_M1 via to overlap with the GND bus. Then draw a rectangle with the BP layer enclosing the via, using the layer 'BP drw'. Note that if your via + BP rectangle is far from the Nfet, it will produce additional problems such as resistance/capacitance between bulk and source/drain. So try to locate it as close as possible in further layouts.

After all this exercise, your layout should look like as below :

 

 

Note that you can view only desired layers by clicking the 'NV' button in your LSW window. Select desired layers by left-clicking, and deselect unwanted layers by right-clicking your mouse. Then go back to your layout screen and repeat Ctrl + f and Shift + f. This is extremely useful when trying to figure out what a cell is composed of, and also locating faulty connections. You can go back to viewing all layers by clicking on the 'AV' button.

Note also that you can add new pins by hitting hitting ctrl + p. If you have deleted a pin by mistake, or want to make new pins, press ctrl + p and define desired properties. Especially watch out for the metal layer, metal type, label size and type (If your pin is of M1 pn material, label your pins with M1 ll).

 

Summary of shortcut keys, in addition to those mentioned in the Tutorial on Schematic Editor :
r --- draw rectangle
w --- draw path
k --- ruler
s + drag cursor onto an edge or corner --- edit edges or corners of a rectangle
m --- move object
shift + f / ctrl + f --- display or not display layout metal contents
F3 in the middle of a function --- options to that function


 

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