parasitic extraction using Calibre PEX
If you haven't read the CAD tool information page, READ THAT FIRST.
In this handout, we will learn how to
extract layout with Calibre PEX and simulate (with Spectre) from the extracted
Now that you have
completed a layout, it is time to find out how good it is. The extraction takes
your layout and makes a more realistic model based on physical-structural
properties. For example, it would make no difference if you had a 100n long wire
or 100u long wire in your schematic, but it would certainly affect its physical
properties (R, C) in your layout, and hence your calibre extraction.
An extraction runs DRC and LVS again, then
models the parasitic components. You can use this extracted model to simulate in
Spectre and compare it with the results from your schematic.
- Before beginning, make sure that you
have run Calibre LVS the layout and the result was "clean".
- First make a directory in your home
directory named 'calibre_pex'.
- IMPORTANT: Go to
Calibre -> Setup -> Calibre View and
enter the following directory next to "Cellmap File".
OK the window.
- To run Calibre PEX, choose the menu
Calibre -> Run PEX.
- Since this is your first time
running PEX, you can hit cancel when you are asked for a 'runset file'. A
runset file saves all of these settings that we are about to change.
- On the PEX form, go to the Rules
tab, and next to PEX Rules File, click the '...' .Go to this directory:
and click on the file named:
- Choose your 'calibre_pex' directory
as your PEX run directory.
- Go to Inputs -> Netlist
and check the Export from schematic viewer bullet.
- In outputs, change the format
from ELDO to CALIBREVIEW. Change use names
from to SCHEMATIC. Set the extraction type to "R + C + CC" to
extract both parasitic capacitors and resistors.
* If you want to be efficient when extracting larger designs, you can use C +
CC to extract only capacitors. Just don't forget that this could lead to fatal
design failures in the real world.
- Now save the above settings by going
to File -> Save Runset. Enter a name like runset1 and OK the new window, and you will be able to reuse the
same settings in the future by loading this runset file.
- Run PEX. It will take close to a
minute for a simple inverter.
- After running, on the "Calibre View
Setup" form that pops up,
- Make sure that your 'Cellmap File'
points to the directory /usr/tech/cms9flp/IBM_PDK/cms9flp/relIBM/Calibre/xRC/cms9flp.calibre.cellmap
- Change "Calibre View Type" to
- Change "Create terminals" to "Create
- Change "Device Placement" to
- Change "Open Calibre Cellview" to
- Hit OK. Warnings are fine, but if
you are getting ERRORs you are in trouble. Check that the pin names and net
names match with the schematic and layout. Go through the steps above from
scratch to make sure you have all of them correctly; one missing step could
easily result in unwanted results.
- If you don't have any ERRORs, you
will see the following screen with a parasitic diode, lots of parasitic
resistors and lots of small parasitic capacitances (to the order of attoFarads
- By zooming into one of the
capacitors, you will be able to see between which nets the capacitance is
- This will then create a "calibre"
view in cadence that is a schematic in Virtuoso, from which you can simulate.
You can locate this together with your schematic, layout, and symbol files in
Now it's time to simulate what we
extracted. Open your 'inverter_test' schematic again. Open your spectre view by
doing Launch -> ADE L . If you have already forgotten about spectre
simulations, refer to: On-line CISL CAD
tutorial on Spectre simulation through the Analog Design Environment (ADE).
Load your saved
state from before which includes library data, temperature, simulation
data, etc. If you have not saved your spectre environment, follow the link above
to go through the settings again. After that we need only change one thing to
simulate our extraction rather than our schematic. Go to
Setup -> Environment and at the topmost line,
enter calibre before
schematic, with a space separating
each word. The window should look like this:
Finally, hit "Netlist and run". Display
your input and output transient results, and you will see a very similar result
from the schematic simulation results. It is because a simple inverter does not
require complicated modeling. Try comparing the two output waveforms and delay