|
| |
 | N. Lei, B. O. Watson, J. N. MacLean, R. Yuste, and K. L.
Shepard, "A 256-by-256 CMOS microelectrode array for extracellular
stimulation of acute brain slices," Proceedings to the International
Solid-State Circuits Conference, 2008 (to appear) |
2007
| B. Calhoun, Y. Cao, X. Li, K. Mai. L. Pileggi, R. A.
Rutenbar, and K. L. Shepard, "Digital circuit design challenges and
opportunities in the era of nanoscale CMOS," Proceedings of the IEEE (to
appear) |
| Z. Xu and K. L. Shepard, "Low-jitter active deskewing
through injection-locked resonant clocking," IEEE Custom Integrated
Circuits Conference, 2007. |
| I. Meric, V. Caruso, R. Caldwell, J. Hone, K. L. Shepard,
and S. J. Wind, "Hybrid carbon nanotube-silicon CMOS circuit," Journal of
Vacuum Science and Technology B (to appear) |
| I. Meric, V. Caruso, R. Caldwell, J. Hone, K. L. Shepard,
and S. J. Wind, "Hybrid carbon nanotube-silicon CMOS circuits,"
Proceedings of the EIPBN, 2007. |
| T.-C. Huang, S. Sorgenfrei, K. L. Shepard, P. Gong, and R. Levicky,
"A CMOS array sensor for sub-800-ps time-resolved
fluorescence detection," IEEE Custom Integrated Circuits Conference,
2007. |
| P. M. Levine, P. Gong, K. L. Shepard, and R. Levicky,
"Active CMOS array for electrochemical sensing of biomolecules,"
IEEE Custom Integrated Circuits Conference, 2007. |
| K. A. Jenkins, K. L. Shepard, and Zheng Xu,
"On-chip circuit for measuring period jitter and skew of
clock distribution networks," IEEE Custom Integrated Circuits
Conference, 2007. |
| V. Wang and K. L. Shepard,
"On-chip transistor characterisation arrays for variability analysis,"
Electronics Letters, Vol. 43, No. 15, July, 19, 2007. |
| D. E. Schwartz, E. Charbon, and K. L. Shepard,
"A single-photon avalanche diode imager for fluorescence
lifetime applications," Symposium on VLSI Circuits, 2007, pp. 144-245. |
| A. P. Jose and K. L. Shepard,
"Distributed loss-compensation techniques for energy-efficient low-latency
on-chip communications," IEEE Journal of Solid-State Circuits, Vol. 42,
June, 2007, pp. 1415-1424. |
2006
| K. L. Shepard and D. N. Maynard, "Variability and yield
improvements: rules, models, and characterization," International Conference
on Computer-Aided Design, 2006. |
| G. Patounakis, K. L. Shepard, and R. Levicky,
"Active CMOS array sensor for time-resolved fluorescence detection," IEEE Journal of
Solid-State Circuits, November, 2006 |
| Y. W. Li, K. L. Shepard, and Y. P. Tsividis,
"A
continuous-time programmable digital FIR filter," IEEE Journal of
Solid-State Circuits, November, 2006 |
| S. C. Chan, K. L. Shepard, and P. J. Restle,
"Distributed differential oscillators for global
clock networks," IEEE Journal of Solid-State Circuits, September, 2006,
pp. 2083-2094. |
| G. Shen, N. Tercero, M. A. Gaspar, B. Varughese, K.
Shepard, and R. Levicky, "Charging behavior of
single-stranded DNA polyelectrolyte brushes," Journal of the American
Chemical Society, Vol. 128, pp. 8427-8433, June, 2006. |
| S. Rajapandian, K. L. Shepard, P. Hazucha, and T. Karnik,
"High-voltage power delivery through charge
recycling," IEEE Journal of Solid-State Circuits, June, 2006, pp.
|
| A. P. Jose, G. Patounakis, and K. L. Shepard,
"Pulse
current-mode signalling for nearly speed-of-light intrachip communications,"
IEEE Journal of Solid-State Circuits, Vol. 41, April, 2006, pp. 772-780. |
| A. P. Jose and K. L. Shepard, "Distributed loss
compensation for low-latency on-chip interconnects," Digest of Technical
Papers, International Solid-State Circuits Conference, 2006. |
2005
| S. Rajapandian, Z. Xu, and K. L. Shepard,
"Implicit dc-dc downconversion
through charge recycling," IEEE Journal of Solid-State Circuit, April, 2005. |
| S. C. Chan, K. L. Shepard, and P. J. Restle,
"Uniform-phase,
uniform-amplitude resonant-load global clock distribution," IEEE Journal of
Solid-State Circuits, January, 2005 |
| A. P. Jose, G. Patounakis, and K. L. Shepard,
"Near speed-of-light
on-chip interconnects using pulsed current-mode signalling," Symposium
on VLSI Circuits, 2005. |
| G. Patounakis, K. L. Shepard, and R. Levicky,
"Active CMOS
biochip for time-resolved fluorescence detection," Symposium on VLSI
Circuits, 2005. |
| Y. W. Li, K. L. Shepard, and Y. P. Tsividis,
"A
continuous-time programmable digital FIR filter," Custom Integrated Circuits
Conference, 2005. |
| Y. P. Tsividis, G. Cowan, Y. W. Li, and K. L. Shepard,
"Continuous-time DSP, Analog/digital computers and other mixed-domain
circuits," European Solid-State Circuits Conference, September, 2005. |
| Y. W. Li, K. L. Shepard, and Y. P. Tsividis,
"Continuous-time digital signal processors," Proceedings of the
International Symposium on Asynchronous Circuits and Systems, 2005, pp.
138-143. |
| S. C. Chan, K. L. Shepard, and P. J. Restle,
"1.1-1.6 GHz distributed
differential oscillator global clock network," Digest of Technical Papers,
International Solid-State Circuits Conference, 2005. |
| S. Rajapandian, K. L. Shepard, P. Hazucha, and T. Karnik,
"High-tension
power delivery: operating 180-nm CMOS digital logic at a 5.4-V supply,"
Digest of Technical Papers, International Solid-State Circuits Conference,
2005 |
2004
| D. Sitaram, Y. Zheng, and K. L. Shepard, ``Full-chip,
three-dimensional, shapes-based RLC extraction," IEEE Transactions on CAD,
May 2004 |
| Y. Li, G. Patounakis, K. L. Shepard, and S. M. Nowick,
"Design of an
asynchronous micropipelined datapath with heterogeneous, dynamic voltage
scaling," IEEE Journal of Solid-State Circuits, April, 2004 |
| G. Patounakis, Y. W. Li, and K. L. Shepard,
"A Fully Integrated On-Chip
DC-DC Conversion and Power Management System," IEEE Journal of Solid-State
Circuits, 2004, March, 2004 |
| S. Rajapandian, Z. Xu, and K. L. Shepard, "Energy-efficient, low-voltage
operation of digital CMOS circuits through charge-recycling," Symposium on
VLSI Circuits, 2004. |
| S. C. Chan, P. J. Restle, K. L. Shepard, N. James, and R. Franch, "A 4.8
GHz Resonant Global Clock Distribution," Digest of Technical Papers,
International Solid-State Circuits Conference, 2004. |
2003
| Y. Zheng and K. L. Shepard, "On-chip oscilloscopes for noninvasive
time-domain measurement of waveforms in digital integrated circuits," IEEE
Transactions on VLSI, June, 2003, pp. 336-344. |
| Y. Li, G. Patounakis, K. L. Shepard,
"High-throughput asynchronous datapath with software-controlled voltage scaling," VLSI Circuits
Symposium, 2003, pp. 49-52. |
| S. C. Chan, K. L. Shepard, and P. J. Restle, "Design of resonant global
clock distributions," Proceedings of International Conference
on Computer Design, 2003. |
| Y. Li, G. Patounakis, A. Jose, K. L. Shepard and S. M. Nowick,
"Asynchronous datapath with software-controlled on-chip adaptive voltage
scaling for multirate signal processing applications, " Proceedings of
the International Symposium on Asynchronous Circuits and Systems, 2003, pp.
216-225. |
| S. Rajapandian, Z. Xu, and K. L. Shepard, "Charge-recycling voltage domains for
energy-efficient low-voltage operation of digital CMOS circuits," Proceedings of International Conference on Computer Design, 2003. |
2002
| Steven C. Chan, K. L. Shepard, and Dae-Jin Kim,
"Static noise analysis for digital integrated circuits in partially
depleted silicon-on-insulator technology," IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, August, 2002,
pages 916-927. |
| Dipak Sitaram, Yu Zheng, and K. L. Shepard,
"Implicit treatment of substrate and power-ground losses in return-limited
inductance extraction," Proceedings of the International Conference on
Computer-Aided Design, 2002, pp. 94-99. |
2001
| K. L. Shepard and D.-J. Kim,
``Body-voltage estimation in digital PD-SOI circuits and its application
to static timing analysis," IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, July, 2001, pages 888-901. |
| Steven Chan and K. L. Shepard,
``Practical considerations in RLCK crosstalk analysis for digital
integrated circuits," Proceedings of the International Conference
on Computer-Aided Design, 2001, pages 598-604 |
| K. L. Shepard and Yu Zheng, "On-chip oscilloscopes for noninvasive
time-domain measurement of waveforms," Proceedings of the International Conference on Computer
Design, September, 2001, pp. 221-226. Best paper award winner |
| K. L. Shepard,
``CAD Issues for CMOS VLSI Design in SOI," Proceedings of the
International Symposium on Quality in Electronic Design, March, 2001,
pages 105-110 (invited) |
2000
| K. L. Shepard and Z. Tian,
``Return-limited inductance: A practical approach to on-chip inductance
extraction," IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, April, 2000, pages 425-436. |
| K. L. Shepard and D.-J. Kim, ``Static
noise analysis for digital integrated circuits in partially-depleted
silicon-on-insulator technology," Proceedings of the Design Automation
Conference, June, 2000, pages 239-242. |
| K. L. Shepard and K. Chou,
``Cell characterization for noise stability," Proceedings of the Custom
Integrated Circuits Conference, 2000, pages 91-94. |
1999 and earlier
|
K. L. Shepard, V. Narayanan, and R. Rose,
``Harmony: A methodology for noise analysis in deep submicron digital
integrated circuits," IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, August, 1999, pages 1132 - 1150.
|
| M. Kamon, S. McCormick, and K. L. Shepard,
``Interconnect Parasitic Extraction in the Digital IC Design Methodology,"
Proceedings of the International Conference on Computer-Aided Design,
1999, pages 223-230. |
| K. L. Shepard and Z. Tian, "Return-limited inductances: A
Practical Approach to On-Chip Inductance Extraction", Proceedings of the
1999 Custom Integrated Circuits Conference. |
| K. L. Shepard and D.-J. Kim,
``Body-voltage estimation in digital PD-SOI circuits and its application
to static timing analysis," Proceedings of the International
Conference on Computer-Aided Design, 1999, pages 531-538 |
| K. L. Shepard and V. Narayanan,
"Conquering noise in deep submicron digital ICs," IEEE Design and Test
of Computers, January-March, 1998. |
| K. L. Shepard, "Design methodologies for noise in digital
integrated circuits," Proceedings of the Design Automation
Conference, 1998, pp. 94-99. |
| K. L. Shepard, "The challenge of
high-performance, deep-submicron design in a turnkey ASIC environment,"
Proceedings of the 1998 International ASIC conference, pp. 183-186. (invited)
|
| C. F. Webb, C. J. Anderson, L. Sigal, K. L. Shepard, J. S. Liptay,
J. D. Warnock, B. Curran, B. W. Krumm, M. D. Mayo, P. J. Camporese, E. M.
Schwarz, M. S. Farrell, P. J. Restle, R. M. Averill III, T. J. Slegel, W. V.
Huott, Y. H. Chan, B. Wile, T. N. Nguyen, P. G. Emma, D. K. Beece, C.-T.
Chuang, and C. Price,
"A 400-MHz S/390 microprocessor," IEEE Journal of Solid-State Circuits,
November, 1997, pages 1665-1675. |
| K. L. Shepard, "Practical Issues of Interconnect Analysis in
Deep Submicron Integrated Circuits," Proceedings of the International
Conference on Computer Design, 1997, pages 532-541 |
| K. L. Shepard, V. Narayanan, P. C. Elmendorf, and Gutuan Zheng,
"Global Harmony: Coupled noise analysis for full-chip RC interconnect
networks," Proceedings of the International Conference on Computer-Aided
Design, 1997, pages 139-146 |
| C. F. Webb, C. J. Anderson, L. Sigal, K. L. Shepard, J. S. Liptay,
J. D. Warnock, B. Curran, B. W. Krumm, M. D. Mayo, P. J. Camporese, E. M.
Schwarz, M .S. Farrell, P. J. Restle, R. M. Averill, III, T. J. Slegel, W.
V. Huott, Y. H. Chan, B. Wile, and P. Emma,
"A 400MHz S/390 Microprocessor," Proceedings of the International
Solid-State Circuits Conference, 1997, pages 168-169. |
| K. L. Shepard, S. Carey, D. K. Beece, R. Hatch, and G. Northrop,
"Design Methodology for the High-Performance G4 3/390
Microprocessor," Proceedings of the International Conference on Computer
Design, 1997, pages 232-240 |
| K. L. Shepard and V. Narayanan,
"Noise in deep submicron digital design," Proceedings of the
International Conference on Computer-Aided Design, 1996, pages 524-531
|
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