Power-management circuits

Delivering power to integrated circuits is becoming an increasingly complex challenge. On the high end, chips can demand in excess of 150 W of power at supply voltages of less than 1 V, leading to current demands approaching 200 A. Furthermore, power supply integrity must generally be assured to within 10% of nominal VDD levels, putting unrealistic targets on power-supply network impedances. We have been working on on-chip DC-DC conversion approaches that allow power to be delivered to chips at higher voltages and lower current levels. One of the techniques we have developed involves "stacking" circuits, as shown in the example below, which allows chips to operate from supply voltages at multiples of the nominal supply voltage. DC-DC downconversion is implicit as charge utilized by one domain is recycled and used by the next domain in the stack.

Related Publications:

• S. Rajapandian, K. L. Shepard, P. Hazucha, and T. Karnik, "High-voltage power delivery through charge recycling," IEEE Journal of Solid-State Circuits, June, 2006
• S. Rajapandian, Z. Xu, and K. L. Shepard, "Implicit dc-dc downconversion through charge recycling," IEEE Journal of Solid-State Circuit, April, 2005
• S. Rajapandian, K. L. Shepard, P. Hazucha, and T. Karnik, "High-tension power delivery: operating 180-nm CMOS digital logic at a 5.4-V supply," Digest of Technical Papers, International Solid-State Circuits Conference, 2005.
• S. Rajapandian, Z. Xu, and K. L. Shepard, "Energy-efficient, low-voltage operation of digital CMOS circuits through charge-recycling," Symposium on VLSI Circuits, 2004