Circuits for intrachip communications and networks-on-chip

Using full-rail interfaces on chip (in which CMOS inverters drive CMOS over RC-dominated interconnect) is a very energy inefficient means of communication (for a given amount of bandwidth density) and results in unnecessarily long wire latencies. We have been developing techniques to take full advantage of the transmission line properties of on-chip wires to achieve high-bandwidth, low-latency, and low-energy on-chip interconnects. One testchip, shown below, uses distributed shunt negative conductance elements to compensate for transmission line losses in a 14-mm long link.

Related Publications

• A. P. Jose and K. L. Shepard, "Distributed loss-compensation techniques for energy-efficient low-latency on-chip communications," IEEE Journal of Solid-State Circuits, Vol. 42, June, 2007, pp. 1415-1424.
• A. P. Jose, G. Patounakis, and K. L. Shepard, "Pulse current-mode signalling for nearly speed-of-light intrachip communications," IEEE Journal of Solid-State Circuits, Vol. 41, April, 2006, pp. 772-780.
• A. P. Jose and K. L. Shepard, "Distributed loss compensation for low-latency on-chip interconnects," Digest of Technical Papers, International Solid-State Circuits Conference, 2006.
• A. P. Jose, G. Patounakis, and K. L. Shepard, "Near speed-of-light on-chip interconnects using pulsed current-mode signalling," Symposium on VLSI Circuits, 2005.