Carbon-based Electronics

Si CMOS is facing increasing challenges in continuing performance gains with channel length scaling due to the growing importance of fringe capacitance parasitics, short-channel effects due to degraded electrostatics, and gate leakage. Silicon technology is focusing on double-gate or finFET technology to improve device parasitics and boost device transconductance, high-k gate dielectrics to reduce gate leakage, and uniaxial strained silicon channels to boost ballistic velocities. At the same time, there has been growing interest in carbon electronics, i.e. carbon nanotubes and graphene, as alternate channel materials for field-effect devices.

Nanotubes are the 1-D structures of carbon atoms with both metallic and semiconducting forms existing. The advantages include ballistic velocities that are potentially 50% higher than what can be achieved in strained silicon and inherently "wrap-around" gating of nanotubes which improves short-channel effects and boosts transconductance per unit device width over what can be achieved in silicon if nanotubes can be packed into dense arrays.

Graphene is a 2-D sheet of carbon atoms and has only very recently been explored as an electronic materal. It is a zero-bandgap semiconductor with a linear E-k dispersion relationship, making it a very unique material. The advantages here, similar to carbon nanotubes, are very high mobilities and saturation velocities and the potential for nearly perfect two-dimensional electrostatics in field-effect devices. Despite the zero-bandgap nature of graphene, field-effect devices with Ion/Ioff ratios of approximately 10 can be constructed and many analog/RF applications of these devices can be pursued.

Many challenges remain in the fabrication of carbon field-effect transistors including relatively poor control over chirality and controlled large area samples for nanotubes. Furthermore, fabricated device structures have poor subthreshold slopes and high parasitic; Schottky-barrier sources and drains also produce high contact resistances. Some progress has been made in these areas including doped contacts and self-aligned device structures, although most of the devices fabricated have been single-nanotube transistors. Graphene FETs (GFET) have other challenges, including the synthesis of large graphene sheets and direct growth of a gate dielectric for more efficient gates with minimal trapped charges.

We have been investigating the DC and high-frequency characteristics of GFETs. We have shown, for the first time, saturating device characteristics and current gains well up to the gigahertz regime. We were also able to develop a device model for these novel FETs.

We have also been developing a hybrid CNFET/CMOS technology performed as a postprocess on a conventional commercial submicron CMOS run. The fabrication process involves a transfer mechanism that allows carbon nanotubes to be grown and optically characterized (to determine the bandgap, Eg, of semiconducting tubes) before being transferred with lithographic precision to a conventional CMOS chip, resulting in a three-dimensional integration with CMOS and CNFET devices "sandwiching" the metal interconnection network. This approach represents a general strategy in which high-performance carbon-based devices could be employed strategically with Si CMOS devices and passives for analog/RF and mixed-signal applications.

Related Publications:

1. I. Meric, N. Baklitskaya, P. Kim, and K. L. Shepard, “RF performance of top-gated graphene field effect transistos’” IEDM 2008 (to be published)
2. I. Meric, M Y. Han, A. F. Young, B. Ozyilmaz, P. Kim, and K. L. Shepard “Current saturation in zero-bandgap, top-gated graphene field-effect transistors” Nature Nanotechnology, 2008 DOI: 10.1038/nnano.2008.268
3. I. Meric, V. Caruso, R. Caldwell, J. Hone, K. L. Shepard, and S. J. Wind, "Hybrid carbon nanotube-silicon complementary metal oxide semiconductor circuits," Journal of Vacuum Science and Technology B 25(6) 2007