Resonant global clock distributions

Clocking large-scale integrated circuits is becoming an increasing challenge. Designing low-skew and low-jitter clock distributions is becoming increasingly difficult in the presence of process, temperature, and voltage variations. We have been designing several generations of prototype resonant clock distributions, which use on-chip spiral inductors to resonate clock loads, reducing the size and number of active elements needed to drive the clock network. Dramatic jitter reductions has been observed in the presence of power supply noise compared with equivalent traditional clock networks of equivalent loading. The figure below is one of our testchips.

Related Publications:

• Z. Xu and K. L. Shepard, "Low-jitter active deskewing through injection-locked resonant clocking," IEEE Custom Integrated Circuits Conference, 2007 (to appear)
• S. C. Chan, K. L. Shepard, and P. J. Restle, "Distributed differential oscillators for global clock networks," IEEE Journal of Solid-State Circuits, September, 2006, pp. 2083-2094.
• S. C. Chan, K. L. Shepard, and P. J. Restle, "Uniform-phase, uniform-amplitude resonant-load global clock distribution," IEEE Journal of Solid-State Circuits, January, 2005
• S. C. Chan, K. L. Shepard, and P. J. Restle, "1.1-1.6 GHz distributed differential oscillator global clock network," Digest of Technical Papers, International Solid-State Circuits Conference, 2005.
• S. C. Chan, P. J. Restle, K. L. Shepard, N. James, and R. Franch, "A 4.8 GHz Resonant Global Clock Distribution," Digest of Technical Papers, International Solid-State Circuits Conference, 2004.