In this design, you will implement an electric piano using field programmable gate arrays (FPGAs). The LSI and MSI gates used to implement the digital logic of the previous labs are largely chips of the past. Digital logic today is implemented in CMOS on VLSI chips -- either programmable microprocessors or microcontroller, application-specific integrated circuits (custom VLSI chips with more limited programmability), or FPGAs, which can be customized to perform specific logic functions through a kind of once at start-up programming. FPGAs are often used to "prototype" designs before committing to an expensive ASIC implementation.
Digital logic today is generally designed not as a netlist of gates but as a logic description that is captured in a hardware description language (HDL). The two most popular HDLs are Verilog and VHDL, the latter of which we use extensively at Columbia.
In Labs 5 and 6, you will learn how "real" digital design is done using VHDL, implemented on a fairly state-of-the-art FPGA. The design we have chosen for this exercise is an electric piano. By using a piezoelectric speaker, which has a fairly high impedance, we can drive it directly from the FPGA. This is a similar approach to what is done on the musical greeting cards. The VHDL description is synthesized to logic and mapped to the gates of the FPGA.
If you are interest in some music theory, please check out the following links:
The schematic of the design is shown below. This is captured in the
file piano.vhd, which you will find in /usr/cad/xilinx/s3_kit_cd/designs/piano/src.
You should copy the contents of this directory to your home directory; for example, to copy
everything to a new directory on your desktop, you can do the following:
cp /usr/cad/xilinx/s3_kit_cd/designs/piano/src ~/Desktop/piano_lab -r
The design consists of the following components:
P How are the notes encoded on the switches?
P If CLK is a 50 MHz input clock, sketch the waveforms on CLK_OUT and ONE_SHOT for EN = '1' and DIV = X"32" (32 in hex, which is equal to 50 in decimal representation). You should also sketch the toggle and trigger waveforms; you can trace these signals one cycle at a time to determine their behavior.
The design uses good synchronous design practice in whcih the output of your clock divider is used as a clock enable. The entire design functions from a signel clock, the timing and distribution of which can be carefully controlled.
P For a 1MHz input, calculate the output frequency as a function of divider value. Combining what you calculate with the table at the top of this document, verify the values used for the note decoder to define the notes of the piano.
By constantly scanning the value of the digits with a low-rate clock you can achieve a persistance of vision similar to a television. Too slow a scan-rate will cause a noticable flicker, however.
This figure from the "Spartan-3 Starter Kit Board User Guide" shows how you will scan each digit in time. Notice that the AN signals are active low.
In this figure you see all the control signals used for the 7-segment display. The design mplements a 7-segment decoder that translates a binary-encoded number into the segments needed for that number.
P Study the implementation in seven_seg.vhd and explain how the design functions.
We will lean how to synthesize this design to the Xilinx FPGAs to implement the piano.
First open the "Programmable Logic Design Quick Start Handbook".
$ cd /usr/cad/xilinx/s3_kit_cd/files $ acroread BeginnnersBook-screen.pdf &
Read these chapters:
Next open the "Spartan-3 Starter Kit Board User Guide"
$ cd /usr/cad/xilinx/s3_kit_cd/files/starterkit $ acroread s3_board_ug.pdf &
Find the exact part number number and package type of the FPGA used on the board.
EXAMPLE: Part number "xc3s4000fg900-4" is decoded as:
part: xc3s4000 -- A large Spartan-3 package: fg900 -- 900 pin ball grid package speed grade: -4
You will need to tell the tools exactly what part you are designing for in the next step.
We'll add source files later. Select NEXT for the next two steps. You should now have the Project Navigator window available.
This is the template you should use for adding a FF in your device. Remember that in synchronous design each FF must have a reset.
Edit --> Preferences [Integrated Tools] Model Tech Simulator --> /usr/cad/modelsim/linux/vsim
To simulate your design, you will create a VHDL file called a testbench. This will instantiate the device-under-test (DUT), generate the clocks, and provide other stimulus to your design for testing.
The following is a basic testbench template....
-- *** Test Bench - User Defined Section *** -- 50MHz system Clock Generation clk_gen: PROCESS BEGIN CLK_IN <= '0'; wait for 10 ns; CLK_IN <= '1'; wait for 10 ns; END PROCESS; -- End clock generation addition tb : PROCESS BEGIN -- System Reset - Sets reset to push_button # 0 pb_in(0) <= '1'; wait for 100 ns; pb_in(0) <= '0'; -- end system reset addition. wait; -- will wait forever END PROCESS; -- *** End Test Bench - User Defined Section ***P Add additional stimulus to test for various values of pb_in and switch_in..
Make sure you save the test bench (Ctrl-S)
P Save some waveforms from your simulation to demonstrate the functionality of the design. Use the ksnapshot tool for screenshots. Use gimp to scale the image if necessary.